1. Field of the Invention
The present invention relates to memory, especially static random access memory (“SRAM”), and more particularly to robust local bit select circuitry for overcoming timing mismatch, and a corresponding method of operation.
2. Description of the Related Art
A static random access memory (“SRAM”) is commonly used in digital electronics systems to provide fast access to locally stored data, such as to data stored in a cache associated with a processor. In typical SRAMs, a memory cell can either be read from or written to in one cycle of the memory. However, dual port SRAMs can have circuitry which permits a single memory cell to be read from and written to at the same time.
Some SRAM designs have a plurality of memory arrays, and include circuitry which allows some of the control signals which operate the SRAM to be utilized by the memory cells of more than one of the memory arrays. For example, in such SRAM, a pair of complementary global signals WRITE GLOBAL BITLINE TRUE (WGBLT) and WRITE GLOBAL BITLINE COMPLEMENT (WGBLC) transmit write global bitline values to a selected one of two or more complementary pairs of read local bitlines READ LOCAL BITLINE TRUE (RLBLT0) and READ LOCAL BITLINE COMPLEMENT (RLBLC0); or another pair of read local bitlines (not shown). In turn, the selected read local bitline pair transmits the bitline write values to a selected memory cell connected to the read local bitline pair.
SRAM designs which include a plurality of memory arrays and which transfer signals from global bitlines to read local bitlines in the above-discussed manner can be subject to timing mismatches in the signals used to control the reading from and writing to of memory cells. The timing mismatch is best discussed with reference to FIG. 1A, which illustrates a local bit-select circuit 10 according to the prior art. With reference to FIG. 1B, particular conventions are followed herein when referring to the respective gate, source and drain terminals of p-type field effect transistors. As referred to herein throughout, the gate terminal of a PFET is identified by reference letter “G”, the source terminal, which is usually connected to a higher voltage than the drain terminal, e.g., supply voltage Vs, is identified by reference “S”, and the drain terminal is identified by reference “D”. These conventions are used throughout, whether or not each such terminal is so marked in the figures. Similarly, as seen in FIG. 1C, and as referred to herein throughout, the gate terminal of an NFET is identified by reference letter “G”, the source terminal, which is usually connected to a lower voltage than the drain terminal, e.g., ground, is identified by reference “S”, and the drain terminal is identified by reference “D”.
As seen in FIG. 1A, a local bit-select circuit includes a pair of pull-up devices 20 or “reset” devices which can be implemented using p-type field effect transistors (“PFETs”) having source terminals connected to a power supply voltage Vdd and drain terminals connected to the respective read local bitlines RLBLT0 and RLBLC0. These devices 20 can be used to pull up the value of the read local bitlines to Vdd prior to reading from or writing to a memory cell connected to the read local bitlines. The power supply voltage Vdd typically is the same as that which supplies power to each of the memory cells (not shown) of the SRAM.
The local bit-select circuit 10 also includes pull-down devices 30, which can be implemented using n-type field effect transistors (“NFETs”), for example. The pull-down devices have gates connected to write global bitlines WGBLT and WGBLC and sources connected to a drain of a write control device 40. During a write operation, the SRAM memory cell is activated to be written, such as by raising a voltage on a wordline connected to the memory cell. At that time, the write global bitlines WGBLT and WGBLC are supplied with write bit values. Then, a write control signal WRT draws current through the write control device 40, which in turn, activates the pull-down devices 30 to cause the bit value on one of RLBLT0 and RLBLC0 to be driven to the low signal level.
However, a problem occurs when there is timing mismatch between some signals. When the write control signal is delayed in relation to the wordline activation, the activated memory cell can operate in a way that resembles a read operation from the selected memory cell. In other words, the delay of the write control signal can cause the value stored in the selected memory cell to begin driving a read signal from the selected memory cell onto one of the read local bitlines. For example, a read signal can drive the bit signal value on one of the pair of read local bitlines RLBLT0 and RLBLC0 to a low signal level. Such problem can be referred to as a “false” read, wherein a strong signal from one of the memory cells on the read local bitlines can interfere with writing the same memory cell.
The read signal appearing on the read local bitline can make it harder to write the new value to the memory cell when the write control signal arrives to begin writing the selected memory cell. For example, if the signal to be written on the read local bitline RLBLT0 is a high signal level, a low signal level appearing as a read signal on RLBLT0 can interfere with driving the high signal level on that read local bitline.
This concern remains inadequately addressed in other local bit-select circuits. One prior art circuit illustrated in FIG. 2 includes a pair of cross-coupled PFETs 50 used to latch the signals on the read local bitlines RLBLT0 and RLBLC0. One effect of such approach is that the cross-coupled PFETs can latch values on the read local bitlines in the interval between a time that RESET is active and when WRT becomes active. Before the WRT signal becomes active, the read local bitlines RLBLT0 and RLBLC0 can have noise thereon or a combination of noise with read signals from the memory cell which is being written at the time. While the cross-coupled PFETs may be able to switch from a state latched prior to the WRT signal to a different state when the WRT signal arrives, the local bitline control circuit may have to work hard to overcome the earlier latched state produced by the cross-coupled PFETs. A potential effect of such approach is that the circuit may need greater current or more time to change the state of the read local bitlines RLBLT0 and RLBLC0 from the state prior to the WRT signal to the state dictated by the WGBLT and WGBLC signals for writing the memory cell.
Another prior art circuit illustrated in FIG. 3 includes a pair of cross-coupled NFETs 60 used to latch values on the read local bitlines RLBLT0 and RLBLC0. As seen in FIG. 3, the cross-coupled NFETs 60 can be supplied at the drains thereof with a column select power supply voltage (Vcs). Such power supply voltage can be raised above the level of the regular power supply (Vdd) to memory cells of the SRAM by an amount of the NFET threshold voltage VT, so that the cross-coupled NFETs 60 can latch signals on the read local bitlines RLBLT0 and RLBLC0 at full rail-to-rail levels. A potential disadvantage of such approach is that the circuit may need greater current or more time to latch the read local bitlines RLBLT0 and RLBLC0 to the states dictated by the WGBLT and WGBLC signals for writing the memory cell.
In view of the foregoing, further improvement would be desirable to address the read-before-write effect which can occur due to timing mismatch in an SRAM.